Stochastic optimization approach to transistor sizing for CMOS VLSI circuits

Sharad Mehrotra, Paul Franzon, Wentai Liu

研究成果: Conference article同行評審

4 引文 斯高帕斯(Scopus)

摘要

A stochastic global optimization approach is presented for transistor sizing in CMOS VLSI circuits. This is a direct search strategy for the best design among feasible ones, with the designer determining when the search is stopped. Through examples, we show the power of this technique in quickly obtaining very good designs, for skew minimization problems.

原文English
頁(從 - 到)36-40
頁數5
期刊Proceedings - Design Automation Conference
DOIs
出版狀態Published - 1994
事件Proceedings of the 31st Design Automation Conference - San Diego, CA, USA
持續時間: 1994 6月 61994 6月 10

All Science Journal Classification (ASJC) codes

  • 硬體和架構
  • 控制與系統工程

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