Strained Si1-xGex graded channel PMOSFET grown by UHVCVD

Chia Yi Su; San Lein Wu; Shoou Jinn Chang; Liang Po Chen

doi:10.1016/S0040-6090(00)00891-9

Strained Si_1-xGe_x graded channel PMOSFET grown by UHVCVD

Chia Yi Su, San Lein Wu, Shoou Jinn Chang, Liang Po Chen

研究成果: Conference article › 同行評審

8 引文斯高帕斯（Scopus）

摘要

The experimental realization of a p-type Si/SiGe heterostructure metal oxide semiconductor field-effect transistor (HMOSFET) structure with a strained Si_1-xGe_x graded well as the conducting channel is reported utilizing ultra-high-vacuum chemical vapor deposition (UHVCVD). The graded variation of the Ge fraction in channel can reduce the relaxation of strained SiGe epilayer. Simultaneously, rapid thermal oxidation (RTO) was used to obtain a high-quality thin-gate oxide films avoiding high thermal budgets which will cause the strain relaxation of graded Si_1-xGe_x layer. The proposed device with a 0.5×100 μm² gate exhibits a well-done transistor behavior. An extrinsic transconductance of 130 mS/mm at room temperature has been obtained.

原文	English
頁（從 - 到）	371-374
頁數	4
期刊	Thin Solid Films
卷	369
發行號	1
DOIs	https://doi.org/10.1016/S0040-6090(00)00891-9
出版狀態	Published - 2000 7月 3
事件	The International Joint Conference on Silicon Epitaxyand Heterostructures (IJC-SI) - Miyagi, Jpn 持續時間: 1999 9月 12 → 1999 9月 17

All Science Journal Classification (ASJC) codes

電子、光磁材料
表面和介面
表面、塗料和薄膜
金屬和合金
材料化學

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10.1016/S0040-6090(00)00891-9

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title = "Strained Si1-xGex graded channel PMOSFET grown by UHVCVD",

abstract = "The experimental realization of a p-type Si/SiGe heterostructure metal oxide semiconductor field-effect transistor (HMOSFET) structure with a strained Si1-xGex graded well as the conducting channel is reported utilizing ultra-high-vacuum chemical vapor deposition (UHVCVD). The graded variation of the Ge fraction in channel can reduce the relaxation of strained SiGe epilayer. Simultaneously, rapid thermal oxidation (RTO) was used to obtain a high-quality thin-gate oxide films avoiding high thermal budgets which will cause the strain relaxation of graded Si1-xGex layer. The proposed device with a 0.5×100 μm2 gate exhibits a well-done transistor behavior. An extrinsic transconductance of 130 mS/mm at room temperature has been obtained.",

author = "Su, {Chia Yi} and Wu, {San Lein} and {Jinn Chang}, Shoou and Chen, {Liang Po}",

note = "Funding Information: This work is supported by the National Science Council of Taiwan ROC under contract NSC87-2215-E-006-003.; The International Joint Conference on Silicon Epitaxyand Heterostructures (IJC-SI) ; Conference date: 12-09-1999 Through 17-09-1999",

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T1 - Strained Si1-xGex graded channel PMOSFET grown by UHVCVD

AU - Su, Chia Yi

AU - Wu, San Lein

AU - Jinn Chang, Shoou

AU - Chen, Liang Po

N1 - Funding Information: This work is supported by the National Science Council of Taiwan ROC under contract NSC87-2215-E-006-003.

PY - 2000/7/3

Y1 - 2000/7/3

N2 - The experimental realization of a p-type Si/SiGe heterostructure metal oxide semiconductor field-effect transistor (HMOSFET) structure with a strained Si1-xGex graded well as the conducting channel is reported utilizing ultra-high-vacuum chemical vapor deposition (UHVCVD). The graded variation of the Ge fraction in channel can reduce the relaxation of strained SiGe epilayer. Simultaneously, rapid thermal oxidation (RTO) was used to obtain a high-quality thin-gate oxide films avoiding high thermal budgets which will cause the strain relaxation of graded Si1-xGex layer. The proposed device with a 0.5×100 μm2 gate exhibits a well-done transistor behavior. An extrinsic transconductance of 130 mS/mm at room temperature has been obtained.

AB - The experimental realization of a p-type Si/SiGe heterostructure metal oxide semiconductor field-effect transistor (HMOSFET) structure with a strained Si1-xGex graded well as the conducting channel is reported utilizing ultra-high-vacuum chemical vapor deposition (UHVCVD). The graded variation of the Ge fraction in channel can reduce the relaxation of strained SiGe epilayer. Simultaneously, rapid thermal oxidation (RTO) was used to obtain a high-quality thin-gate oxide films avoiding high thermal budgets which will cause the strain relaxation of graded Si1-xGex layer. The proposed device with a 0.5×100 μm2 gate exhibits a well-done transistor behavior. An extrinsic transconductance of 130 mS/mm at room temperature has been obtained.

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U2 - 10.1016/S0040-6090(00)00891-9

DO - 10.1016/S0040-6090(00)00891-9

M3 - Conference article

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SN - 0040-6090

VL - 369

SP - 371

EP - 374

JO - Thin Solid Films

JF - Thin Solid Films

IS - 1

T2 - The International Joint Conference on Silicon Epitaxyand Heterostructures (IJC-SI)

Y2 - 12 September 1999 through 17 September 1999

ER -

Strained Si1-xGex graded channel PMOSFET grown by UHVCVD

摘要

All Science Journal Classification (ASJC) codes

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Strained Si_1-xGe_x graded channel PMOSFET grown by UHVCVD