Structural fault based specification reduction for testing analog circuits

Soon Jyh Chang, Chung Len Lee, Jwu E. Chen

研究成果: Article同行評審

8 引文 斯高帕斯(Scopus)

摘要

Specification reduction can reduce test time, consequently, test cost. In this paper, a methodology to reduce specifications during specification testing for analog circuit is proposed and demonstrated. It starts with first deriving relationships between specifications and parameter variations of the circuit-under-test (CUT) and then reduces specifications by considering bounds of parameter variations. A statistical approach by taking into account of circuit fabrication process fluctuation is also employed and the result shows that the specification reduction depends on the testing confidence. A continuous-time state-variable benchmark filter circuit is applied with this methodology to demonstrate the effectiveness of the approach.

原文English
頁(從 - 到)571-581
頁數11
期刊Journal of Electronic Testing: Theory and Applications (JETTA)
18
發行號6
DOIs
出版狀態Published - 2002 十二月

All Science Journal Classification (ASJC) codes

  • 電氣與電子工程

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