Study of capacitor energising transient limiter with a half-wave rectifying compensating voltage system

H. T. Tseng, J. F. Chen

研究成果: Article同行評審

5 引文 斯高帕斯(Scopus)

摘要

This study presents a capacitor energising transient limiter (CETL) with a half-wave rectifying compensating voltage system. The proposed CETL provides a transient inductance to restrain capacitor energising transients at the instant of energisation. After completing the restraint, the limiter provides zero impedance based on the compensating voltage principle, and the capacitor seems to be connected directly to the system voltage source without requiring any control. Therefore in the steady state the capacitor current and voltage waveforms are undistorted, and no voltage rise occurs across the capacitor terminals. Further, this study offers a comparison of the levels of the total harmonic distortion (THD) in the capacitor voltage and current that occurs when different kinds of compensating voltage systems are used, and the relationship between THD and the resistance of the limiting reactor for the proposed CETL is simulated and discussed. In addition, this study also discusses that when the proposed CETL is applied to the low-voltage (LV) capacitor, voltage magnification appears on the capacitor because of the switching of the high-voltage (HV) utility capacitor. During the study period, a single-phase 220 V 0.9 kVAR capacitor was developed for demonstration, and the proposed method is verified by theory, in simulated results, and in field tests.

原文English
頁(從 - 到)1217-1225
頁數9
期刊IET Power Electronics
5
發行號7
DOIs
出版狀態Published - 2012 8月

All Science Journal Classification (ASJC) codes

  • 電氣與電子工程

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