Pipeline technique is the major method to increase the performance of single processor, but when processing branch instructions, we must wait the result of branch to decide the next instruction; we call the waiting time 'Branch Penalty', which will influence the performance of pipeline processor. Branch target buffer is an important method to resolve the branch penalty, but branch penalty occurs when the prediction incorrect. In this paper, we will propose a method to reduce the branch penalty when the prediction falls into an error on branch target buffer.
|出版狀態||Published - 1995 1月 1|
|事件||Proceedings of the IEEE 1st International Conference on Algorithms and Architectures for Parallel Processing. Part 1 (of 2) - Brisbane, Aust|
持續時間: 1995 4月 19 → 1995 4月 21
|Other||Proceedings of the IEEE 1st International Conference on Algorithms and Architectures for Parallel Processing. Part 1 (of 2)|
|期間||95-04-19 → 95-04-21|
All Science Journal Classification (ASJC) codes
- 工程 (全部)