Study on bump arrangement to accelerate the underfill flow in flip-chip packaging

Shih Wei Lin, Wen Bin Young

研究成果: Article同行評審

5 引文 斯高帕斯(Scopus)

摘要

Flip-chip packaging is an integrated circuit packaging technique that uses solder bumps to connect chip with substrate. The underfill process uses epoxy encapsulant to solve this problem and improves the reliability of flip-chip packaging. The encapsulant is filled into the gap between the chip and substrate by the capillary force so that the thermal stresses may disperse into the underfill materials to avoid crack generation. The filling time in the underfill process strongly depends on the arrangement of the solder bumps. The edge effect can enhance the filling speed during the underfill encapsulation if the void formation can be avoided. With distributed bump pitch design, the filling time of the underfill can be reduced. There exists an optimal selection of the pitch variation during the use of distributed bump pitch. Another method of using a center bump-free channel can also increase the filling efficiency. The optimization method is used to determine the size of the channel that is found to increase the filling speed dramatically in the case of underfill of the chip with a fine bump pitch.

原文English
文章編號6363586
頁(從 - 到)40-45
頁數6
期刊IEEE Transactions on Components, Packaging and Manufacturing Technology
3
發行號1
DOIs
出版狀態Published - 2013

All Science Journal Classification (ASJC) codes

  • 電子、光磁材料
  • 工業與製造工程
  • 電氣與電子工程

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