Sub-40nm V-groove MOSFETs

J. Appenzeller, R. Martel, Ph Avouris, J. Knoch, Y. Lu, K. L. Wang, J. Scholvin, J. A. Del Alamo, P. Rice, P. Solomon

研究成果: Paper同行評審

1 引文 斯高帕斯(Scopus)

摘要

The V-groove MOSFETs capable of generating high performance transistor characteristics of sub-40 nm was demonstrated. MOSFETs with source and drain separation down to Lg=36 nm exhibiting a definite state of electric characteristics were presented. The output characteristics of 36 nm V-groove MOSFET, the corresponding sub-threshold and transfer characteristics as well as characteristics for V-groove openings were discussed. The intrinsic output resistance was also calculated.

原文English
頁面95-96
頁數2
出版狀態Published - 2001
事件Device Research Conference (DRC) - Notre Dame, IN, United States
持續時間: 2001 六月 252001 六月 27

Conference

ConferenceDevice Research Conference (DRC)
國家/地區United States
城市Notre Dame, IN
期間01-06-2501-06-27

All Science Journal Classification (ASJC) codes

  • 工程 (全部)

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