This paper presents an efficient synchronous pipeline hardware implementation procedure for a neuro-fuzzy (NF) circuit. We decompose the NF circuit into a feedforward circuit and a backpropagation circuit. The concept of pre-calculation to share computation results between the feedforward circuit and backpropagation circuit is introduced to achieve a high throughput rate and low resource usage. A novel pipeline architecture has been adopted to fulfill the concept of pre-calculation. With the unique pipeline architecture, we have successfully enhanced the throughput rate and resource sharing between modules. Particularly, the multiplier usage has been reduced from 7 to 3 and the divider usage from 3 to 1. Finally, we have implemented the NF circuit on FGPA. Our experimental results show a superior performance than that of an asynchronous pipeline design approach and the NF system implemented on MATLAB®.