Synthesis of Application-Specific Highly Efficient Multi-Mode Cores for Embedded Systems

Lih Yih Chiou, Swarup Bhunia, Kaushik Roy

研究成果: Article同行評審

20 引文 斯高帕斯(Scopus)

摘要

In this paper, we present a novel design methodology for synthesizing multiple configurations (or modes) into a single programmable core that can be used in embedded systems. Recent portable applications require reconfigurability of a system along with efficiency in terms of power, performance, and area. The field programmable gate arrays (FPGAs) provide a reconfigurable platform; however, they are slower in speed with significantly higher power and area than achievable by a customized application-specific integrated circuits (ASIC). Implementation of a system in either FPGA or ASIC represents a trade-off between programmability and design efficiency. In this work, we have developed techniques to realize efficient reconfigurable cores for a set of user-specified applications. The resultant system, named as multimode system, can easily switch configurations throughout the set of configurations it is designed for. A data flow graph transformation method coupled with efficient scheduling and allocation is used to automatically synthesize a Multi-Mode system from its behavior-level specifications. Experimental results on several applications demonstrate that our implementations can achieve about 60X power reduction on average and run 3.5X faster over corresponding FPGA implementations.

原文English
頁(從 - 到)168-188
頁數21
期刊ACM Transactions on Embedded Computing Systems
4
發行號1
DOIs
出版狀態Published - 2005 二月 1

All Science Journal Classification (ASJC) codes

  • 軟體
  • 硬體和架構

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