Synthesizable wide range DPWM with all-digital PLL for digitally-controlled switching converter

Chun Hung Yang; Mu Chin-Wei Mu; Chien-Hung Tsai

doi:10.1109/IECON.2011.6119550

Synthesizable wide range DPWM with all-digital PLL for digitally-controlled switching converter

Chun Hung Yang, Mu Chin-Wei Mu, Chien-Hung Tsai

電機工程學系

研究成果: Conference contribution

3 引文斯高帕斯（Scopus）

摘要

This paper proposes a synthesizable digital pulse-width modulator (DPWM) architecture, which combines conventional hybrid DPWM with all-digital phase-locked loop (ADPLL) schemes. The digitally controlled oscillator (DCO) of the ADPLL shares hardware with the delay line in the hybrid DPWM to reduce cost. The ADPLL allows the proposed DPWM to accurately calibrate its operating frequency (i.e., the switching frequency) to counteract the delay lines' process, voltage, and temperature (PVT) effects in a wide frequency range. An FPGA prototype DPWM and its associated digitally controlled buck converter system are implemented to verify the proposed architecture.

原文	English
主出版物標題	Proceedings
主出版物子標題	IECON 2011 - 37th Annual Conference of the IEEE Industrial Electronics Society
頁面	1626-1630
頁數	5
DOIs	https://doi.org/10.1109/IECON.2011.6119550
出版狀態	Published - 2011 12月 1
事件	37th Annual Conference of the IEEE Industrial Electronics Society, IECON 2011 - Melbourne, VIC, Australia 持續時間: 2011 11月 7 → 2011 11月 10

出版系列

名字	IECON Proceedings (Industrial Electronics Conference)

Other

Other	37th Annual Conference of the IEEE Industrial Electronics Society, IECON 2011
國家/地區	Australia
城市	Melbourne, VIC
期間	11-11-07 → 11-11-10

All Science Journal Classification (ASJC) codes

控制與系統工程
電氣與電子工程

存取文件

10.1109/IECON.2011.6119550

其它文件與鏈接

引用此

Yang, C. H., Chin-Wei Mu, M., & Tsai, C.-H. (2011). Synthesizable wide range DPWM with all-digital PLL for digitally-controlled switching converter. 於 Proceedings: IECON 2011 - 37th Annual Conference of the IEEE Industrial Electronics Society (頁 1626-1630). 文章 6119550 (IECON Proceedings (Industrial Electronics Conference)). https://doi.org/10.1109/IECON.2011.6119550

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title = "Synthesizable wide range DPWM with all-digital PLL for digitally-controlled switching converter",

abstract = "This paper proposes a synthesizable digital pulse-width modulator (DPWM) architecture, which combines conventional hybrid DPWM with all-digital phase-locked loop (ADPLL) schemes. The digitally controlled oscillator (DCO) of the ADPLL shares hardware with the delay line in the hybrid DPWM to reduce cost. The ADPLL allows the proposed DPWM to accurately calibrate its operating frequency (i.e., the switching frequency) to counteract the delay lines' process, voltage, and temperature (PVT) effects in a wide frequency range. An FPGA prototype DPWM and its associated digitally controlled buck converter system are implemented to verify the proposed architecture.",

author = "Yang, {Chun Hung} and {Chin-Wei Mu}, Mu and Chien-Hung Tsai",

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doi = "10.1109/IECON.2011.6119550",

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}

Yang, CH, Chin-Wei Mu, M & Tsai, C-H 2011, Synthesizable wide range DPWM with all-digital PLL for digitally-controlled switching converter. 於 Proceedings: IECON 2011 - 37th Annual Conference of the IEEE Industrial Electronics Society., 6119550, IECON Proceedings (Industrial Electronics Conference), 頁 1626-1630, 37th Annual Conference of the IEEE Industrial Electronics Society, IECON 2011, Melbourne, VIC, Australia, 11-11-07. https://doi.org/10.1109/IECON.2011.6119550

TY - GEN

T1 - Synthesizable wide range DPWM with all-digital PLL for digitally-controlled switching converter

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AU - Chin-Wei Mu, Mu

AU - Tsai, Chien-Hung

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Y1 - 2011/12/1

N2 - This paper proposes a synthesizable digital pulse-width modulator (DPWM) architecture, which combines conventional hybrid DPWM with all-digital phase-locked loop (ADPLL) schemes. The digitally controlled oscillator (DCO) of the ADPLL shares hardware with the delay line in the hybrid DPWM to reduce cost. The ADPLL allows the proposed DPWM to accurately calibrate its operating frequency (i.e., the switching frequency) to counteract the delay lines' process, voltage, and temperature (PVT) effects in a wide frequency range. An FPGA prototype DPWM and its associated digitally controlled buck converter system are implemented to verify the proposed architecture.

AB - This paper proposes a synthesizable digital pulse-width modulator (DPWM) architecture, which combines conventional hybrid DPWM with all-digital phase-locked loop (ADPLL) schemes. The digitally controlled oscillator (DCO) of the ADPLL shares hardware with the delay line in the hybrid DPWM to reduce cost. The ADPLL allows the proposed DPWM to accurately calibrate its operating frequency (i.e., the switching frequency) to counteract the delay lines' process, voltage, and temperature (PVT) effects in a wide frequency range. An FPGA prototype DPWM and its associated digitally controlled buck converter system are implemented to verify the proposed architecture.

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SN - 9781612849720

T3 - IECON Proceedings (Industrial Electronics Conference)

SP - 1626

EP - 1630

BT - Proceedings

T2 - 37th Annual Conference of the IEEE Industrial Electronics Society, IECON 2011

Y2 - 7 November 2011 through 10 November 2011

ER -

Synthesizable wide range DPWM with all-digital PLL for digitally-controlled switching converter

摘要

出版系列

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All Science Journal Classification (ASJC) codes

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