Synthesizable wide range DPWM with all-digital PLL for digitally-controlled switching converter

Chun Hung Yang, Mu Chin-Wei Mu, Chien-Hung Tsai

研究成果: Conference contribution

3 引文 斯高帕斯(Scopus)

摘要

This paper proposes a synthesizable digital pulse-width modulator (DPWM) architecture, which combines conventional hybrid DPWM with all-digital phase-locked loop (ADPLL) schemes. The digitally controlled oscillator (DCO) of the ADPLL shares hardware with the delay line in the hybrid DPWM to reduce cost. The ADPLL allows the proposed DPWM to accurately calibrate its operating frequency (i.e., the switching frequency) to counteract the delay lines' process, voltage, and temperature (PVT) effects in a wide frequency range. An FPGA prototype DPWM and its associated digitally controlled buck converter system are implemented to verify the proposed architecture.

原文English
主出版物標題Proceedings
主出版物子標題IECON 2011 - 37th Annual Conference of the IEEE Industrial Electronics Society
頁面1626-1630
頁數5
DOIs
出版狀態Published - 2011 十二月 1
事件37th Annual Conference of the IEEE Industrial Electronics Society, IECON 2011 - Melbourne, VIC, Australia
持續時間: 2011 十一月 72011 十一月 10

出版系列

名字IECON Proceedings (Industrial Electronics Conference)

Other

Other37th Annual Conference of the IEEE Industrial Electronics Society, IECON 2011
國家Australia
城市Melbourne, VIC
期間11-11-0711-11-10

All Science Journal Classification (ASJC) codes

  • Control and Systems Engineering
  • Electrical and Electronic Engineering

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