System development of time triggered dual CAN bus system for small aircraft avionics

Digital avionics using integrated module avionics (IMA) has made the system architecture simplified and operation flexible to carry digital data access. Digital data bus system using controller area network (CAN) for small aircrafts has superior accidental event capability [1]. However, the predictability on data transmission still requires enforcement. The arbitration mechanism in CAN has assigned higher priority to those high frequency data or important flight data. CAN bus have some drawbacks such as unpredictable delays on lower priority message and data lose under high bus load operation. The time trigger mechanism can be added onto CAN mechanism by TTCAN chip to improve the time scheduling in periodic data transmission [2], but it is strict and complex to synchronize the time sequence. To enhance the function of CAN bus and improve its stability and reliability, a dual CAN bus is proposed to extend the original single bus prototype in hardware and software [3]. Consequently, the complexity in time sequence synchronization in TTCAN chip has brought significant development effort on dual data bus system. This paper classifies the data frequency and assigns a new timing concept to implement this dual CAN bus system. The application of time trigger concept on dual CAN bus system is found to improve its performance.