System-level development and verification framework for high-performance system accelerator

Chen Chieh Wang, Ro Pun Wong, Jing Wun Lin, Chung-Ho Chen

研究成果: Conference contribution

18 引文 斯高帕斯(Scopus)

摘要

In this paper, we propose a framework to develop high-performance system accelerator at system-level. This framework is designed by integrating a virtual machine, an electronic system level platform, and an enhanced QEMU-SystemC. The enhancement includes a local master interface for fast memory transfer, and an interrupt handling hardware for software/hardware communication support that enables full system simulation. We have also developed a network virtual interface for our system to co-work with the real world network environment. Finally, the MD5 algorithm offload and the network offload engine are used as examples to demonstrate the proposed framework system for full system simulation.

原文English
主出版物標題2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09
頁面359-362
頁數4
DOIs
出版狀態Published - 2009 十二月 1
事件2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09 - Hsinchu, Taiwan
持續時間: 2009 四月 282009 四月 30

出版系列

名字2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09

Other

Other2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09
國家/地區Taiwan
城市Hsinchu
期間09-04-2809-04-30

All Science Journal Classification (ASJC) codes

  • 硬體和架構
  • 控制與系統工程
  • 電氣與電子工程

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