A bit-level systolic array for RSA public key cryptosystem is designed based on our modified Montgomery's algorithm. Since the post adjustment in the original algorithm is removed, the modified algorithm leads to both simpler architecture and better performance. A prototype CMOS VLSI chip was designed and simulated, which implements a 512-bit RSA cryptosystem. This chip can achieve an encryption (or decryption) rate of 24.3 Kb/sec under a 50 MHz clock.
|頁（從 - 到）||408-411|
|期刊||Proceedings - IEEE International Symposium on Circuits and Systems|
|出版狀態||Published - 1996 一月 1|
|事件||Proceedings of the 1996 IEEE International Symposium on Circuits and Systems, ISCAS. Part 1 (of 4) - Atlanta, GA, USA|
持續時間: 1996 五月 12 → 1996 五月 15
All Science Journal Classification (ASJC) codes