Systolic RSA public key cryptosystem

Po Song Chen; Shih Arn Hwang; Cheng Wen Wu

Systolic RSA public key cryptosystem

Po Song Chen, Shih Arn Hwang, Cheng Wen Wu

電機工程學系

研究成果: Conference article › 同行評審

31 引文斯高帕斯（Scopus）

摘要

A bit-level systolic array for RSA public key cryptosystem is designed based on our modified Montgomery's algorithm. Since the post adjustment in the original algorithm is removed, the modified algorithm leads to both simpler architecture and better performance. A prototype CMOS VLSI chip was designed and simulated, which implements a 512-bit RSA cryptosystem. This chip can achieve an encryption (or decryption) rate of 24.3 Kb/sec under a 50 MHz clock.

原文	English
頁（從 - 到）	408-411
頁數	4
期刊	Proceedings - IEEE International Symposium on Circuits and Systems
卷	4
出版狀態	Published - 1996 1月 1
事件	Proceedings of the 1996 IEEE International Symposium on Circuits and Systems, ISCAS. Part 1 (of 4) - Atlanta, GA, USA 持續時間: 1996 5月 12 → 1996 5月 15

All Science Journal Classification (ASJC) codes

電氣與電子工程
電子、光磁材料

其它文件與鏈接

引用此

@article{f330d236bb6c41c3bba9348cf822c79f,

title = "Systolic RSA public key cryptosystem",

abstract = "A bit-level systolic array for RSA public key cryptosystem is designed based on our modified Montgomery's algorithm. Since the post adjustment in the original algorithm is removed, the modified algorithm leads to both simpler architecture and better performance. A prototype CMOS VLSI chip was designed and simulated, which implements a 512-bit RSA cryptosystem. This chip can achieve an encryption (or decryption) rate of 24.3 Kb/sec under a 50 MHz clock.",

author = "Chen, {Po Song} and Hwang, {Shih Arn} and Wu, {Cheng Wen}",

year = "1996",

month = jan,

day = "1",

language = "English",

volume = "4",

pages = "408--411",

journal = "Proceedings - IEEE International Symposium on Circuits and Systems",

issn = "0271-4310",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

note = "Proceedings of the 1996 IEEE International Symposium on Circuits and Systems, ISCAS. Part 1 (of 4) ; Conference date: 12-05-1996 Through 15-05-1996",

}

TY - JOUR

T1 - Systolic RSA public key cryptosystem

AU - Chen, Po Song

AU - Hwang, Shih Arn

AU - Wu, Cheng Wen

PY - 1996/1/1

Y1 - 1996/1/1

N2 - A bit-level systolic array for RSA public key cryptosystem is designed based on our modified Montgomery's algorithm. Since the post adjustment in the original algorithm is removed, the modified algorithm leads to both simpler architecture and better performance. A prototype CMOS VLSI chip was designed and simulated, which implements a 512-bit RSA cryptosystem. This chip can achieve an encryption (or decryption) rate of 24.3 Kb/sec under a 50 MHz clock.

AB - A bit-level systolic array for RSA public key cryptosystem is designed based on our modified Montgomery's algorithm. Since the post adjustment in the original algorithm is removed, the modified algorithm leads to both simpler architecture and better performance. A prototype CMOS VLSI chip was designed and simulated, which implements a 512-bit RSA cryptosystem. This chip can achieve an encryption (or decryption) rate of 24.3 Kb/sec under a 50 MHz clock.

UR - http://www.scopus.com/inward/record.url?scp=0029698376&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0029698376&partnerID=8YFLogxK

M3 - Conference article

AN - SCOPUS:0029698376

SN - 0271-4310

VL - 4

SP - 408

EP - 411

JO - Proceedings - IEEE International Symposium on Circuits and Systems

JF - Proceedings - IEEE International Symposium on Circuits and Systems

T2 - Proceedings of the 1996 IEEE International Symposium on Circuits and Systems, ISCAS. Part 1 (of 4)

Y2 - 12 May 1996 through 15 May 1996

ER -

Systolic RSA public key cryptosystem

摘要

All Science Journal Classification (ASJC) codes

其它文件與鏈接

指紋

引用此