Systolic RSA public key cryptosystem

Po Song Chen, Shih Arn Hwang, Cheng Wen Wu

研究成果: Conference article同行評審

30 引文 斯高帕斯(Scopus)

摘要

A bit-level systolic array for RSA public key cryptosystem is designed based on our modified Montgomery's algorithm. Since the post adjustment in the original algorithm is removed, the modified algorithm leads to both simpler architecture and better performance. A prototype CMOS VLSI chip was designed and simulated, which implements a 512-bit RSA cryptosystem. This chip can achieve an encryption (or decryption) rate of 24.3 Kb/sec under a 50 MHz clock.

原文English
頁(從 - 到)408-411
頁數4
期刊Proceedings - IEEE International Symposium on Circuits and Systems
4
出版狀態Published - 1996 一月 1
事件Proceedings of the 1996 IEEE International Symposium on Circuits and Systems, ISCAS. Part 1 (of 4) - Atlanta, GA, USA
持續時間: 1996 五月 121996 五月 15

All Science Journal Classification (ASJC) codes

  • 電氣與電子工程
  • 電子、光磁材料

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