We present a parallel-in parallel-out systolic division circuit over GF(2/sup m/) based on the novel extended Stein's algorithm that provides guaranteed convergence in 2/sup m/-1 iterations. The area-time (AT) complexity of our design is O(m/sup 2/) and the achievable maximum clock rate is 1 GHz based on the 0.6 /spl mu/m technology. Compared to the best systolic design known to date based on the extended Euclid's algorithm the proposed circuit exhibits significant area and speed advantages.
|主出版物標題||ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings|
|出版狀態||Published - 2001|
|事件||2001 IEEE International Symposium on Circuits and Systems, ISCAS 2001 - Sydney, NSW, Australia|
持續時間: 2001 五月 6 → 2001 五月 9
|Other||2001 IEEE International Symposium on Circuits and Systems, ISCAS 2001|
|期間||01-05-06 → 01-05-09|
All Science Journal Classification (ASJC) codes