Systolic VLSI realization of a novel iterative division algorithm over GF(2): A high-speed, low-complexity design

Chien Hsing Wu, Chien Ming Wu, Ming-Der Shieh, Yin Tsung Hwang

研究成果: Conference contribution

14 引文 斯高帕斯(Scopus)

摘要

We present a parallel-in parallel-out systolic division circuit over GF(2/sup m/) based on the novel extended Stein's algorithm that provides guaranteed convergence in 2/sup m/-1 iterations. The area-time (AT) complexity of our design is O(m/sup 2/) and the achievable maximum clock rate is 1 GHz based on the 0.6 /spl mu/m technology. Compared to the best systolic design known to date based on the extended Euclid's algorithm the proposed circuit exhibits significant area and speed advantages.

原文English
主出版物標題ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings
頁面33-36
頁數4
4
DOIs
出版狀態Published - 2001
事件2001 IEEE International Symposium on Circuits and Systems, ISCAS 2001 - Sydney, NSW, Australia
持續時間: 2001 五月 62001 五月 9

Other

Other2001 IEEE International Symposium on Circuits and Systems, ISCAS 2001
國家/地區Australia
城市Sydney, NSW
期間01-05-0601-05-09

All Science Journal Classification (ASJC) codes

  • 硬體和架構
  • 電氣與電子工程

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