Test algorithm and bist design for mram write disturbance fault

Ching Yi Chen, Wan Yu Lo, Chin Lung Su, Cheng Wen Wu

研究成果: Article同行評審

1 引文 斯高帕斯(Scopus)

摘要

The write disturbance fault (WDF) model is a fault model specific to MRAM which implies that the data stored in the MRAM cells is changed due to excessive magnetic field during a Write operation. March tests have high coverage for conventional RAM faults. However, they do not detect all WDFs. To improve the quality and yield of MRAM, we propose a new test algorithm to detect WDF for MRAM in this paper, and further apply the proposed algorithm to test MRAM chips. Fault coverage of proposed test algorithm is higher than that of traditional March test algorithms. Also, we develop a built-in self-test (BIST) circuit that supports the proposed test method. A 128Kb MRAM prototype chip with proposed BIST circuit has been designed and fabricated using a special 0.15 um CMOS technology.

原文English
頁(從 - 到)63-70
頁數8
期刊International Journal of Electrical Engineering
15
發行號2
出版狀態Published - 2008 4月 1

All Science Journal Classification (ASJC) codes

  • 電氣與電子工程

指紋

深入研究「Test algorithm and bist design for mram write disturbance fault」主題。共同形成了獨特的指紋。

引用此