Test compression

Xiaowei Li, Kuen-Jong Lee, Nur A. Touba

研究成果: Chapter

1 引文 斯高帕斯(Scopus)

摘要

This chapter introduces the the basic concepts and principles of test compression. Test compression involves compressing the amount of test data (both stimulus and response) that must be stored on automatic test equipment (ATE) for testing with a deterministic (automatic test pattern generation [ATPG]-generated) test set. The idea in test compression is to compress the amount of test data (both stimulus and response) that is stored on the tester. This provides two advantages: the first is that it reduces the amount of tester memory that is required, and the second advantage is that it reduces test time because less test data has to be transferred across the low bandwidth link between the tester and the chip. The chapter focuses on test stimulus compression and describes three different categories of schemes: using data compression codes, employing linear decompression, and broadcasting the same value to multiple scan chains. Moreover some additional on-chip hardware before the scan chains to decompress the test stimulus coming from the tester and after the scan chains to compact the response going to the tester are also used to test compression. Finally test response compaction and different ways for dealing with unknown (non-deterministic) values in the output response along with the commercial tools used for implementing test compression in industry are discussed.

原文English
主出版物標題VLSI Test Principles and Architectures
發行者Elsevier Inc.
頁面341-396
頁數56
ISBN(列印)9780123705976
DOIs
出版狀態Published - 2006 十二月 1

All Science Journal Classification (ASJC) codes

  • Business, Management and Accounting(all)

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  • 引用此

    Li, X., Lee, K-J., & Touba, N. A. (2006). Test compression. 於 VLSI Test Principles and Architectures (頁 341-396). Elsevier Inc.. https://doi.org/10.1016/B978-012370597-6/50010-X