Test pattern generation and clock disabling for simultaneous test time and power reduction

Jih Jeen Chen, Chia Kai Yang, Kuen Jong Lee

研究成果: Article同行評審

23 引文 斯高帕斯(Scopus)

摘要

Scan-based design has been widely used to transport test patterns in a system-on-a-chip (SOC) test architecture. Two problems that are becoming quite critical for scan-based testing are long test application time and high test power consumption. Previously, many efficient methods have been developed to address these two problems separately. In this paper, we propose a novel method called the multiple clock disabling (MCD) technique to reduce test application time and test power dissipation simultaneously. Our method is made possible by cleverly modifying and integrating a number of existing techniques to generate a special set of test patterns that is suitable for a scan architecture based on the MCD technique. Experimental results for the International Symposium on Circuits and Systems (ISCAS)'85 and '89 benchmark circuits show that significant reduction on both test application time and power dissipation can be achieved compared to the conventional scan method.

原文English
頁(從 - 到)363-369
頁數7
期刊IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
22
發行號3
DOIs
出版狀態Published - 2003 三月

All Science Journal Classification (ASJC) codes

  • 軟體
  • 電腦繪圖與電腦輔助設計
  • 電氣與電子工程

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