Test scheduling and test access architecture optimization for system-on-chip

Huan Shan Hsu, Jing Reng Huang, Kuo Liang Cheng, Chih Wea Wang, Chih Tsun Huang, Cheng Wen Wu, Youn Long Lin

研究成果: Conference contribution

15 引文 斯高帕斯(Scopus)

摘要

We propose an efficient test scheduling and test access architecture for system-on-chip. The test time and test control complexity are optimized under the test power and test access mechanism (TAM) resource constraints. Using our heuristic algorithms, the test scheduling can be done rapidly with small test time penalty when compared with previous works. Under an existing SoC test framework, the test access hardware can be generated from the scheduling result. Experimental results show that the proposed scheduling is hardware efficient. The system integrator can evaluate the test access architecture and perform rest scheduling systematically.

原文English
主出版物標題Proceedings of the 11th Asian Test Symposium, ATS 2002
發行者IEEE Computer Society
頁面411-416
頁數6
ISBN(電子)0769518257, 0769518257
DOIs
出版狀態Published - 2002 一月 1
事件11th Asian Test Symposium, ATS 2002 - Guam, United States
持續時間: 2002 十一月 182002 十一月 20

出版系列

名字Proceedings of the Asian Test Symposium
2002-January
ISSN(列印)1081-7735

Other

Other11th Asian Test Symposium, ATS 2002
國家/地區United States
城市Guam
期間02-11-1802-11-20

All Science Journal Classification (ASJC) codes

  • 電氣與電子工程

指紋

深入研究「Test scheduling and test access architecture optimization for system-on-chip」主題。共同形成了獨特的指紋。

引用此