Test Stimulus Compression Based on Broadcast Scan with One Single Input

Jhen Zong Chen, Kuen Jong Lee

研究成果: Article同行評審

11 引文 斯高帕斯(Scopus)

摘要

In this paper, a novel test compression technique is proposed that can achieve very high test compression ratio with low area overhead and only one single test input. An inverter and a series of D flip-flops together with a configurable switch logic are inserted between the single input and the scan chains so as to convert the input patterns to the test data required by each scan chain. All scan chains are divided into some scan groups such that scan chains in the same group can share the same test data and the switch logic only needs to connect each group to an appropriate data provider. Hence the total area overhead is quite small. A novel algorithm is developed to determine the required test configurations and corresponding test patterns for 100% testable fault coverage. Experimental results show that on average this method can achieve data reduction factors of 23×, 124×, and 394 × with 3.77%, 0.95%, and 0.03% area overhead for ISCAS'89, IWLS'05 OpenCores, and IWLS'05 Gaisler Research benchmark circuits, respectively. These results indicate that the reduction factor increases with the sizes of circuits; it even reaches 464 × for a circuit containing 2.07 million gates with very small area overhead. As all test and control data can be provided by a single input, great reduction on test channel requirement is also achieved.

原文English
文章編號7463526
頁(從 - 到)184-197
頁數14
期刊IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
36
發行號1
DOIs
出版狀態Published - 2017 一月

All Science Journal Classification (ASJC) codes

  • 軟體
  • 電腦繪圖與電腦輔助設計
  • 電氣與電子工程

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