We propose a novel C-testable technique for the fast-Fourier-transform (FFT) networks. Only 18 test patterns are required to achieve 100% coverage of combinational single cell faults and interconnect stuck-at faults for the FFT network. A fault tolerant design for the FFT network also has been proposed. Compared with previous results, our approach has higher reliability and lower hardware overhead - only three spare bit-level cells are needed for repairing a faulty row in the multiply-subtract-add (MSA) module, and special cell design is not required to implement the reconfiguration scheme. The hardware overhead is low - about 4% for 16-bit numbers regardless of the FFT network size.
|頁（從 - 到）||201-209|
|期刊||IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems|
|出版狀態||Published - 1999 十二月 1|
|事件||Proceedings of the 1999 IEEE International Symposium on Defect and Faulttolerance in VLSI Systems (DFT'99) - Albueqeurque, NM, USA|
持續時間: 1999 十一月 1 → 1999 十一月 3
All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering