Testable and fault tolerant design for FFT networks

Jin Fu Li, Cheng Wen Wu

研究成果: Conference contribution

摘要

We propose a novel C-testable technique for the fast-Fourier-transform (FFT) networks. Only 18 test patterns are required to achieve 100% coverage of combinational single cell faults and interconnect stuck-at faults for the FFT network. A fault tolerant design for the FFT network also has been proposed. Compared with previous results, our approach has higher reliability and lower hardware overhead-only three spare bit-level cells are needed for repairing a faulty row in the multiply-subtract-add (MSA) module, and special cell design is not required to implement the reconfiguration scheme. The hardware overhead is low-about 4% for 16-bit numbers regardless of the FFT network size.

原文English
主出版物標題Proceedings - 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 1999
發行者Institute of Electrical and Electronics Engineers Inc.
頁面201-209
頁數9
ISBN(電子)076950325X, 9780769503257
DOIs
出版狀態Published - 1999 1月 1
事件1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 1999 - Albuquerque, United States
持續時間: 1999 11月 11999 11月 3

出版系列

名字Proceedings - 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 1999

Conference

Conference1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 1999
國家/地區United States
城市Albuquerque
期間99-11-0199-11-03

All Science Journal Classification (ASJC) codes

  • 硬體和架構
  • 電氣與電子工程
  • 安全、風險、可靠性和品質

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