NBTI (Negative Bias Temperature Instability), which can degrade the switching speed of PMOS transistors, has become a major reliability challenge. Meanwhile, reducing leakage consumption has become major design goals. In this paper, we propose a novel transmission gate-based (TG) technique to minimize NBTI-induced degradation and leakage. This technique provides higher flexibility compared to the gate replacement technique. Simulation results show our proposed technique has up to 20X and 2.44X on average improvement on NBTI-induced degradation with comparable leakage power reduction. With a 19% area penalty, combining our technique and the gate replacement can reduce 19.39% of the total leakage power and 36.56% of the NBTI-induced circuit degradation.