The cathode current efficiency of flip-chip solder bump plating

Kwang-Lung Lin, Yeh Hsiu Liu

研究成果: Article同行評審

4 引文 斯高帕斯(Scopus)

摘要

Flip chip solder bumps were produced on various bump pad dimensions by electroplating to investigate their current efficiency. The bump pad dimensions range from 60 × 60 μm to 250 × 250 μm. Bump heights are in the range of 80-150 μm. The bump height achieved is very uniform across a 4 in. wafer. The growth of bump height follows a parabolic trend with respect to plating time. Experimental results showed that the cathode current efficiency increases with increasing pad size. The cathode current efficiency also increases with respect to plating time and approaches a constant level after 30 min of deposition.

原文English
期刊Journal of the Electrochemical Society
150
發行號8
DOIs
出版狀態Published - 2003 八月 1

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Renewable Energy, Sustainability and the Environment
  • Surfaces, Coatings and Films
  • Electrochemistry
  • Materials Chemistry

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