The influence of the layout on the ESD performance Of HV-LDMOS

Jian Hsing Lee, Hung Der Su, Chien Ling Chan, D. H. Yang, Jone F. Chen, K. M. Wu

研究成果: Conference contribution

36 引文 斯高帕斯(Scopus)

摘要

The root causes of the high voltage (HV) LDMOS (Fig. 2) failed at the low voltage electrostatic-discharge (ESD) zap is found. One is caused by the bulk layout and one is caused by the intrinsic characteristic of the device. From the findings, a new structure is proposed to eliminate the root causes without sacrificing the IV characteristics and dimension of the device.

原文English
主出版物標題2010 22nd International Symposium on Power Semiconductor Devices and IC's, ISPSD 2010
頁面303-306
頁數4
出版狀態Published - 2010 9月 20
事件2010 22nd International Symposium on Power Semiconductor Devices and IC's, ISPSD 2010 - Hiroshima, Japan
持續時間: 2010 6月 62010 6月 10

出版系列

名字Proceedings of the International Symposium on Power Semiconductor Devices and ICs
ISSN(列印)1063-6854

Other

Other2010 22nd International Symposium on Power Semiconductor Devices and IC's, ISPSD 2010
國家/地區Japan
城市Hiroshima
期間10-06-0610-06-10

All Science Journal Classification (ASJC) codes

  • 工程 (全部)

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