@inproceedings{23a27b0702454a0094645ecc2926c85f,
title = "The influence of the layout on the ESD performance Of HV-LDMOS",
abstract = "The root causes of the high voltage (HV) LDMOS (Fig. 2) failed at the low voltage electrostatic-discharge (ESD) zap is found. One is caused by the bulk layout and one is caused by the intrinsic characteristic of the device. From the findings, a new structure is proposed to eliminate the root causes without sacrificing the IV characteristics and dimension of the device.",
author = "Lee, {Jian Hsing} and Su, {Hung Der} and Chan, {Chien Ling} and Yang, {D. H.} and Chen, {Jone F.} and Wu, {K. M.}",
year = "2010",
month = sep,
day = "20",
language = "English",
isbn = "9781424477180",
series = "Proceedings of the International Symposium on Power Semiconductor Devices and ICs",
pages = "303--306",
booktitle = "2010 22nd International Symposium on Power Semiconductor Devices and IC's, ISPSD 2010",
note = "2010 22nd International Symposium on Power Semiconductor Devices and IC's, ISPSD 2010 ; Conference date: 06-06-2010 Through 10-06-2010",
}