The performance and experimental results of a multiple bit rate symbol timing recovery circuit for PSK receivers

Mehmet R. Yuce, Wentai Liu, Bhaskar Bharat, John Damiano, Paul D. Franzon

研究成果: Conference article同行評審

3 引文 斯高帕斯(Scopus)

摘要

A low-power all-digital symbol timing recovery circuit for digital PSK transmission systems is implemented in a 0.35-μm Silicon On Insulator (SOI) technology. The symbol timing circuit is designed for a wide range of bit rates (0.1-100 Kbps) and robust against fast and large Doppler shift or frequency error on the input signal. The system is therefore well-suited for receivers in deep-space and satellite applications. It is synchronized within 3 or 4 bits and the total power dissipation of the circuit is only 310 μW.

原文English
頁(從 - 到)591-594
頁數4
期刊Proceedings of the Custom Integrated Circuits Conference
出版狀態Published - 2004
事件Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, CICC - Orlando, FL, United States
持續時間: 2004 10月 32004 10月 6

All Science Journal Classification (ASJC) codes

  • 電氣與電子工程

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