The performance and experimental results of a multiple bit rate symbol timing recovery circuit for PSK receivers

Mehmet R. Yuce; Wentai Liu; Bhaskar Bharat; John Damiano; Paul D. Franzon

The performance and experimental results of a multiple bit rate symbol timing recovery circuit for PSK receivers

Mehmet R. Yuce
, Wentai Liu
, Bhaskar Bharat
, John Damiano
, Paul D. Franzon

生物醫學工程學系

研究成果: Conference article › 同行評審

3 引文斯高帕斯（Scopus）

摘要

A low-power all-digital symbol timing recovery circuit for digital PSK transmission systems is implemented in a 0.35-μm Silicon On Insulator (SOI) technology. The symbol timing circuit is designed for a wide range of bit rates (0.1-100 Kbps) and robust against fast and large Doppler shift or frequency error on the input signal. The system is therefore well-suited for receivers in deep-space and satellite applications. It is synchronized within 3 or 4 bits and the total power dissipation of the circuit is only 310 μW.

原文	English
頁（從 - 到）	591-594
頁數	4
期刊	Proceedings of the Custom Integrated Circuits Conference
出版狀態	Published - 2004
事件	Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, CICC - Orlando, FL, United States 持續時間: 2004 10月 3 → 2004 10月 6

All Science Journal Classification (ASJC) codes

電氣與電子工程

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@article{6b9864c52c9d4a91a3dd4b736d4a9923,

title = "The performance and experimental results of a multiple bit rate symbol timing recovery circuit for PSK receivers",

abstract = "A low-power all-digital symbol timing recovery circuit for digital PSK transmission systems is implemented in a 0.35-μm Silicon On Insulator (SOI) technology. The symbol timing circuit is designed for a wide range of bit rates (0.1-100 Kbps) and robust against fast and large Doppler shift or frequency error on the input signal. The system is therefore well-suited for receivers in deep-space and satellite applications. It is synchronized within 3 or 4 bits and the total power dissipation of the circuit is only 310 μW.",

author = "Yuce, \{Mehmet R.\} and Wentai Liu and Bhaskar Bharat and John Damiano and Franzon, \{Paul D.\}",

year = "2004",

language = "English",

pages = "591--594",

journal = "Proceedings of the Custom Integrated Circuits Conference",

issn = "0886-5930",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

note = "Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, CICC ; Conference date: 03-10-2004 Through 06-10-2004",

}

TY - JOUR

T1 - The performance and experimental results of a multiple bit rate symbol timing recovery circuit for PSK receivers

AU - Yuce, Mehmet R.

AU - Liu, Wentai

AU - Bharat, Bhaskar

AU - Damiano, John

AU - Franzon, Paul D.

PY - 2004

Y1 - 2004

N2 - A low-power all-digital symbol timing recovery circuit for digital PSK transmission systems is implemented in a 0.35-μm Silicon On Insulator (SOI) technology. The symbol timing circuit is designed for a wide range of bit rates (0.1-100 Kbps) and robust against fast and large Doppler shift or frequency error on the input signal. The system is therefore well-suited for receivers in deep-space and satellite applications. It is synchronized within 3 or 4 bits and the total power dissipation of the circuit is only 310 μW.

AB - A low-power all-digital symbol timing recovery circuit for digital PSK transmission systems is implemented in a 0.35-μm Silicon On Insulator (SOI) technology. The symbol timing circuit is designed for a wide range of bit rates (0.1-100 Kbps) and robust against fast and large Doppler shift or frequency error on the input signal. The system is therefore well-suited for receivers in deep-space and satellite applications. It is synchronized within 3 or 4 bits and the total power dissipation of the circuit is only 310 μW.

UR - https://www.scopus.com/pages/publications/17044382569

UR - https://www.scopus.com/pages/publications/17044382569#tab=citedBy

M3 - Conference article

AN - SCOPUS:17044382569

SN - 0886-5930

SP - 591

EP - 594

JO - Proceedings of the Custom Integrated Circuits Conference

JF - Proceedings of the Custom Integrated Circuits Conference

T2 - Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, CICC

Y2 - 3 October 2004 through 6 October 2004

ER -

The performance and experimental results of a multiple bit rate symbol timing recovery circuit for PSK receivers

摘要

All Science Journal Classification (ASJC) codes

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