The study of sensitive circuit and layout for CDM improvement

Jian Hsing Lee, J. R. Shih, Shawn Guo, Dao Hong Yang, Jone F. Chen, David Su, Kenneth Wu

研究成果: Conference contribution

16 引文 斯高帕斯(Scopus)

摘要

The influence of the internal circuit layout on the chip CDM performance is reported in this paper. It is found that the well pick-up has great impact on the chip CDM performance. The well pick-up can sink the CDM current into the P-Well and induce the non-uniform current to stress the device. This paper also verifies that the bus-line capacitors are more important than the package capacitor for chip CDM since the well pick-up only can affect the current coming from bus line capacitors, but cannot affect the current coming from the package capacitor. Moreover, putting the circuit and ESD protection device in the deep-NWell to isolate the circuit from the P-substrate and using the long contact-to-contact space for ESD protection device also can get the better CDM performance.

原文English
主出版物標題Proceedings of the 2009 16th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2009
頁面228-232
頁數5
DOIs
出版狀態Published - 2009
事件2009 16th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2009 - Suzhou, China
持續時間: 2009 7月 62009 7月 10

出版系列

名字Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA

Other

Other2009 16th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2009
國家/地區China
城市Suzhou
期間09-07-0609-07-10

All Science Journal Classification (ASJC) codes

  • 電氣與電子工程

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