The use of Mahalanobis-Taguchi System to improve flip-chip bumping height inspection efficiency

Taho Yang, Yuan Ting Cheng

研究成果: Article同行評審

25 引文 斯高帕斯(Scopus)

摘要

With the electronics industry advancing rapidly toward faster, smaller, lighter, and cheaper products, flip-chip packaging has been extensively used in microelectronics. The interconnection of the flip-chip offers several advantages over the widely used wire bonding technique. To obtain a reliable interconnection of the flip-chip, it is important to maintain adequate height of bumps that are plated on the chips. The bump height inspection process is time-consuming in practice and often becomes a constraint during production. The present study aims at solving the bump height inspection efficiency problem. Mahalanobis-Taguchi System (MTS) method is used to reduce the number of bump height measurement points whilst maintaining a high-accuracy inspection level. The results indicate that the numbers of bump height inspection features are significantly reduced from 10 to 6 without losing classification accuracy; and inspection time can be reduced by 40%. By reduction of inspection features, the operation time of the bump height inspection process is reduced. Moreover, the inspection staff can select the inspection position in sequence, according to the significance of features selected by the MTS method. Moreover, they can reduce the number of inspection positions to achieve an acceptable height of bumps.

原文English
頁(從 - 到)407-414
頁數8
期刊Microelectronics Reliability
50
發行號3
DOIs
出版狀態Published - 2010 三月 1

All Science Journal Classification (ASJC) codes

  • 電子、光磁材料
  • 原子與分子物理與光學
  • 安全、風險、可靠性和品質
  • 凝聚態物理學
  • 表面、塗料和薄膜
  • 電氣與電子工程

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