The VLSI technique for state estimation enhancement in power systems

The advancement of very large scale integration (VLSI) techniques has overcome some computation bottlenecks in computer applications, and resulted in improved execution speeds. This paper applies VLSI techniques to state estimation matrix triangulation enhancement in power systems. The systolic array processor is used with a dedicated structure for implementation. The proposed configuration is depicted and described. For different but compatible numerical types, the intermediate processor is taken into account. The proposed method improves the computation speed with high potential for application to many power system problems. Simulations and comparisons of the proposed method with the conventional method support the better characteristics of the systolic array for state estimation.