Thermal-Aware Fixed-Outline Floorplanning Using Analytical Models with Thermal-Force Modulation

Jai Ming Lin, Tai Ting Chen, Hao Yuan Hsieh, Ya Ting Shyu, Yeong Jar Chang, Juin Ming Lu

研究成果: Article同行評審

摘要

High temperature or temperature nonuniformity has become a serious threat to performance and reliability of high-performance integrated circuits (ICs), which makes the thermal effect turn into a nonignorable issue in the circuit design or the physical design. In order to estimate temperature accurately, the locations of modules have to be determined in advance, which makes an efficient and effective thermal-aware floorplanning play a more important role. Hence, this article proposes a differentiable nonlinear placement model that can optimize temperature and minimize wirelength at the same time without needing to construct a congestion map. In addition, to avoid inducing longer wirelength while optimizing temperature, we propose some techniques, such as thermal-aware clustering, shrink of hot modules, or thermal-force modulation in the multilevel framework. The experimental results demonstrate that temperature and wirelength are greatly improved by our method compared to Corblivar. More importantly, our runtime is quite fast and the fixed-outline constraint can also be satisfied.

原文English
文章編號9378550
頁(從 - 到)985-997
頁數13
期刊IEEE Transactions on Very Large Scale Integration (VLSI) Systems
29
發行號5
DOIs
出版狀態Published - 2021 五月

All Science Journal Classification (ASJC) codes

  • 軟體
  • 硬體和架構
  • 電氣與電子工程

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