Thermal resistance of side by side multi-chip package: Thermal mode analysis

Dao Long Chen, Tei Chen Chen, Ping Feng Yang, Yi Shao Lai

研究成果: Article同行評審

9 引文 斯高帕斯(Scopus)


The thermal mode analysis is used in this paper to optimize the thermal management with optimal locations and chip sizes for multi-chip package. The average thermal resistance is defined and analyzed. The spreading thermal resistance can be expanded into Fourier series so that the thermal modes can be established. For the infinite thermal modes, only a few terms are needed to be considered due to the rapid convergence of solution. The optimal locations and chip sizes can then be determined by using the first few modes to reduce the thermal resistance as minimal as possible. The optimal locations have the cosine wave property so that the wave nodes might be the suitable sites. On the other hand, the optimal chip sizes have the cardinal sine property which decays monotonously. For given optimal locations, the optimal chip sizes are determined by certain modes. These special modes can be used to analyze the range of optimal locations and chip sizes.

頁(從 - 到)822-831
期刊Microelectronics Reliability
出版狀態Published - 2015 四月 1

All Science Journal Classification (ASJC) codes

  • 電子、光磁材料
  • 原子與分子物理與光學
  • 凝聚態物理學
  • 安全、風險、可靠性和品質
  • 表面、塗料和薄膜
  • 電氣與電子工程


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