Threshold tuning method for arrays of split-gate nanostructure transistors in series

  • Haider Al-Taie
  • , Luke W. Smith
  • , Reuben K. Puddy
  • , Patrick See
  • , Jonathan P. Griffiths
  • , Ian Farrer
  • , Geb A.C. Jones
  • , David A. Ritchie
  • , Charles G. Smith
  • , Michael J. Kelly

研究成果: Conference contribution

摘要

This paper presents a method to tune an arbitrary number of split-gate transistors in series to their threshold voltage, prior to initiating any particular experiment. The model accounts for device variations and considers coupled/uncoupled electrical gates and ballistic/ohmic addition of resistances. Experimental verification of this 'zeroing method' is provided by detailed conductance measurements through a two-dimensional electron gas formed in a GaAs/AlGaAs heterostructure with two split-gate transistors in series and is extended to zero an array of up to nine split gates in series.

原文English
主出版物標題Proceedings of the IEEE Conference on Nanotechnology
發行者Institute of Electrical and Electronics Engineers Inc.
頁面490-493
頁數4
ISBN(電子)9781479956227
DOIs
出版狀態Published - 2014 11月 26
事件2014 14th IEEE International Conference on Nanotechnology, IEEE-NANO 2014 - Toronto, Canada
持續時間: 2014 8月 182014 8月 21

出版系列

名字Proceedings of the IEEE Conference on Nanotechnology
ISSN(電子)1944-9399

Conference

Conference2014 14th IEEE International Conference on Nanotechnology, IEEE-NANO 2014
國家/地區Canada
城市Toronto
期間14-08-1814-08-21

All Science Journal Classification (ASJC) codes

  • 電氣與電子工程
  • 電腦科學應用
  • 建模與模擬
  • 儀器

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