Threshold-voltage variability analysis and modeling for junctionless double-gate transistors

Chun Yu Chen, Jyi Tsong Lin, Meng Hsueh Chiang

研究成果: Article同行評審

5 引文 斯高帕斯(Scopus)

摘要

This paper presents a detailed analysis on the variation sources in junctionless double-gate transistors using numerical device simulation. Comparison with conventional ultra-scaled devices is also included in the study. When channel thickness is reduced to 10 nm or below, thickness variation becomes a significant source of threshold voltage variation even though random dopant fluctuation has been considered the most significant one, especially in the highly doped junctionless channel. When accounting for volume inversion in the thin silicon film, we propose a modeling approach to estimate the film thickness variation impact on threshold voltage using effective film thickness. Our study suggests that when TSi is less than 4 nm, the threshold voltage becomes less sensitive to film thickness variation, partly due to quantum confinement.

原文English
頁(從 - 到)22-26
頁數5
期刊Microelectronics Reliability
74
DOIs
出版狀態Published - 2017 七月

All Science Journal Classification (ASJC) codes

  • 電子、光磁材料
  • 原子與分子物理與光學
  • 安全、風險、可靠性和品質
  • 凝聚態物理學
  • 表面、塗料和薄膜
  • 電氣與電子工程

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