Tile-based GPU optimizations through ESL full system simulation

Hsu Yao Huang, Chi Yuan Huang, Chung Ho Chen

研究成果: Paper同行評審

1 引文 斯高帕斯(Scopus)

摘要

We present a tile-based GPU design which is modeled in a full system simulation platform. The full system simulation platform includes a functional Linux-based system on which the GPU is incorporated for design explorations. To accurately estimate the execution time of the application graphics software, an execution time synchronization mechanism for the virtual platform is developed. We extend the Ericsson Texture Compression (ETC) scheme in our GPU to support alpha compression. In this way, we are able to reduce the external memory accesses to about one sixth, and speed up the rasterization engine (RE) by 35%. We also optimize the hardware-and-software data flow through the full system design platform and obtain significant improvements.

原文English
頁面1327-1330
頁數4
DOIs
出版狀態Published - 2012 九月 28
事件2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012 - Seoul, Korea, Republic of
持續時間: 2012 五月 202012 五月 23

Other

Other2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012
國家/地區Korea, Republic of
城市Seoul
期間12-05-2012-05-23

All Science Journal Classification (ASJC) codes

  • 硬體和架構
  • 電氣與電子工程

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