Timing-Driven Analytical Placement According to Expected Cell Distribution Range

Jai Ming Lin, You Yu Chang, Wei Lun Huang

研究成果: Conference contribution

摘要

Since the multilevel framework with the analytical approach has been proven as a promising method to handle the very-large-scale integration (VLSI) placement problem, this paper presents two techniques including a pin-connectivity-aware cluster score function and identification of expected object distribution ranges to further improve the coarsening and refinement stages of this framework. Moreover, we extend the proposed analytical placement method to consider timing in order to speed up design convergence. To optimize timing without increasing wirelength, our approach only increases the weights of timing-critical nets, where the weight of a net is estimated according to the associated timing slack and degree. Besides, we propose a new equation to update net weights based on their historical values to maintain the stability of the net-based timing-driven placement approach. Experimental results demonstrate that the proposed analytical placement approach with new techniques can actually improve wirelength of the classic approach. Moreover, our TDP can get much better WNS and TNS than the previous timing-driven placers such as DREAMPlace4.0 and Differentiable TDP.

原文English
主出版物標題ISPD 2024 - Proceedings of the 2024 International Symposium on Physical Design
發行者Association for Computing Machinery
頁面177-184
頁數8
ISBN(電子)9798400704178
DOIs
出版狀態Published - 2024 3月 12
事件33rd International Symposium on Physical Design, ISPD 2024 - Taipei, Taiwan
持續時間: 2024 3月 122024 3月 15

出版系列

名字Proceedings of the International Symposium on Physical Design

Conference

Conference33rd International Symposium on Physical Design, ISPD 2024
國家/地區Taiwan
城市Taipei
期間24-03-1224-03-15

All Science Journal Classification (ASJC) codes

  • 電氣與電子工程

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