Token scan cell for low power testing

T. C. Huang, K. J. Lee

研究成果: Article同行評審

5 引文 斯高帕斯(Scopus)

摘要

A multiphase clocking technique is presented for reducing the test power for scan-based circuits. A novel scan cell design called the token scan cell is developed, which combines a phase-generating flip-flop and a data flip-flop to overcome the inter-phase skew and clock routing problems. Experimental results show that on average ∼87% of the data transition count during scanning is reduced. For many circuits with long chains, a reduction of >98% can even be achieved.

原文English
頁(從 - 到)678-679
頁數2
期刊Electronics Letters
37
發行號11
DOIs
出版狀態Published - 2001 五月 24

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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