Tolerance of performance degrading faults for effective yield improvement

Tong Yu Hsieh, Melvin A. Breuer, Murali Annavaram, Sandeep K. Gupta, Kuen-Jong Lee

研究成果: Conference contribution

23 引文 斯高帕斯(Scopus)

摘要

To provide a new avenue for improving yield for nanoscale fabrication processes, we introduce a new notion: performance degrading faults (pdef). A fault is said to be a pdef if it cannot cause a functional error at system outputs but may result in system performance degradation. In a processor, a fault is a pdef if it causes no error in the execution of user programs but may reduce performance, e.g., decrease the number of instructions executed per cycle. By identifying faulty chips that contain pdef's that degrade performance within some limits and binning these chips based on the their resulting instruction throughput, effective yield can be improved in a radically new manner that is completely different from the current practice of performance binning on clock frequency. To illustrate the potential benefits of this notion, we analyze the faults in the branch prediction unit of a processor. Experimental results show that every stuck-at fault in this unit is a pdef. Furthermore, 97% of these faults induce almost no performance degradation.

原文English
主出版物標題International Test Conference, ITC 2009 - Proceedings
DOIs
出版狀態Published - 2009 十二月 15
事件International Test Conference, ITC 2009 - Austin, TX, United States
持續時間: 2009 十一月 12009 十一月 6

出版系列

名字Proceedings - International Test Conference
ISSN(列印)1089-3539

Other

OtherInternational Test Conference, ITC 2009
國家/地區United States
城市Austin, TX
期間09-11-0109-11-06

All Science Journal Classification (ASJC) codes

  • 電氣與電子工程
  • 應用數學

指紋

深入研究「Tolerance of performance degrading faults for effective yield improvement」主題。共同形成了獨特的指紋。

引用此