Top-down methodology based low-dropout regulator design using Verilog-A

Chia Cheng Pao; Yan Chih Chen; Chien-Hung Tsai

doi:10.1109/ICSICT.2014.7021500

Top-down methodology based low-dropout regulator design using Verilog-A

Chia Cheng Pao, Yan Chih Chen, Chien-Hung Tsai

電機工程學系

研究成果: Conference contribution

2 引文斯高帕斯（Scopus）

摘要

This paper presents a top-down design methodology, which adopts the analog modeling methodology and mixed-level simulation strategy together, for low-dropout regulators (LDO) with low ESR output capacitor. The proposed methodology helps designers to verify the sub-block specifications before designing transistors and reduce design iterations, benefiting cost optimization. All the macro-models are developed in Verilog-A under a Cadence Spectre platform and used in the design flow. A design case implemented in TSMC 0.35μm CMOS technology is presented that shows how this methodology supports system design. Simulation and measurement results expose high similarity, making it a useful and efficient way for LDO design.

原文	English
主出版物標題	Proceedings - 2014 IEEE 12th International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2014
編輯	Jia Zhou, Ting-Ao Tang
發行者	Institute of Electrical and Electronics Engineers Inc.
ISBN（電子）	9781479932962
DOIs	https://doi.org/10.1109/ICSICT.2014.7021500
出版狀態	Published - 2014 1月 23
事件	2014 12th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2014 - Guilin, China 持續時間: 2014 10月 28 → 2014 10月 31

出版系列

名字	Proceedings - 2014 IEEE 12th International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2014

Other

Other	2014 12th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2014
國家/地區	China
城市	Guilin
期間	14-10-28 → 14-10-31

All Science Journal Classification (ASJC) codes

硬體和架構
電氣與電子工程
電腦科學應用

存取文件

10.1109/ICSICT.2014.7021500

其它文件與鏈接

引用此

Pao, C. C., Chen, Y. C., & Tsai, C.-H. (2014). Top-down methodology based low-dropout regulator design using Verilog-A. 於 J. Zhou, & T.-A. Tang (編輯), Proceedings - 2014 IEEE 12th International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2014 文章 7021500 (Proceedings - 2014 IEEE 12th International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2014). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ICSICT.2014.7021500

Pao, Chia Cheng ; Chen, Yan Chih ; Tsai, Chien-Hung. / Top-down methodology based low-dropout regulator design using Verilog-A. Proceedings - 2014 IEEE 12th International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2014. 編輯 / Jia Zhou ; Ting-Ao Tang. Institute of Electrical and Electronics Engineers Inc., 2014. (Proceedings - 2014 IEEE 12th International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2014).

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title = "Top-down methodology based low-dropout regulator design using Verilog-A",

abstract = "This paper presents a top-down design methodology, which adopts the analog modeling methodology and mixed-level simulation strategy together, for low-dropout regulators (LDO) with low ESR output capacitor. The proposed methodology helps designers to verify the sub-block specifications before designing transistors and reduce design iterations, benefiting cost optimization. All the macro-models are developed in Verilog-A under a Cadence Spectre platform and used in the design flow. A design case implemented in TSMC 0.35μm CMOS technology is presented that shows how this methodology supports system design. Simulation and measurement results expose high similarity, making it a useful and efficient way for LDO design.",

author = "Pao, {Chia Cheng} and Chen, {Yan Chih} and Chien-Hung Tsai",

year = "2014",

month = jan,

day = "23",

doi = "10.1109/ICSICT.2014.7021500",

language = "English",

series = "Proceedings - 2014 IEEE 12th International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2014",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

editor = "Jia Zhou and Ting-Ao Tang",

booktitle = "Proceedings - 2014 IEEE 12th International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2014",

address = "United States",

note = "2014 12th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2014 ; Conference date: 28-10-2014 Through 31-10-2014",

}

Pao, CC, Chen, YC & Tsai, C-H 2014, Top-down methodology based low-dropout regulator design using Verilog-A. 於 J Zhou & T-A Tang (編輯), Proceedings - 2014 IEEE 12th International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2014., 7021500, Proceedings - 2014 IEEE 12th International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2014, Institute of Electrical and Electronics Engineers Inc., 2014 12th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2014, Guilin, China, 14-10-28. https://doi.org/10.1109/ICSICT.2014.7021500

Top-down methodology based low-dropout regulator design using Verilog-A. / Pao, Chia Cheng; Chen, Yan Chih; Tsai, Chien-Hung.
Proceedings - 2014 IEEE 12th International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2014. 編輯 / Jia Zhou; Ting-Ao Tang. Institute of Electrical and Electronics Engineers Inc., 2014. 7021500 (Proceedings - 2014 IEEE 12th International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2014).

研究成果: Conference contribution

TY - GEN

T1 - Top-down methodology based low-dropout regulator design using Verilog-A

AU - Pao, Chia Cheng

AU - Chen, Yan Chih

AU - Tsai, Chien-Hung

PY - 2014/1/23

Y1 - 2014/1/23

N2 - This paper presents a top-down design methodology, which adopts the analog modeling methodology and mixed-level simulation strategy together, for low-dropout regulators (LDO) with low ESR output capacitor. The proposed methodology helps designers to verify the sub-block specifications before designing transistors and reduce design iterations, benefiting cost optimization. All the macro-models are developed in Verilog-A under a Cadence Spectre platform and used in the design flow. A design case implemented in TSMC 0.35μm CMOS technology is presented that shows how this methodology supports system design. Simulation and measurement results expose high similarity, making it a useful and efficient way for LDO design.

AB - This paper presents a top-down design methodology, which adopts the analog modeling methodology and mixed-level simulation strategy together, for low-dropout regulators (LDO) with low ESR output capacitor. The proposed methodology helps designers to verify the sub-block specifications before designing transistors and reduce design iterations, benefiting cost optimization. All the macro-models are developed in Verilog-A under a Cadence Spectre platform and used in the design flow. A design case implemented in TSMC 0.35μm CMOS technology is presented that shows how this methodology supports system design. Simulation and measurement results expose high similarity, making it a useful and efficient way for LDO design.

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DO - 10.1109/ICSICT.2014.7021500

M3 - Conference contribution

AN - SCOPUS:84946687257

T3 - Proceedings - 2014 IEEE 12th International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2014

BT - Proceedings - 2014 IEEE 12th International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2014

A2 - Zhou, Jia

A2 - Tang, Ting-Ao

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 2014 12th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2014

Y2 - 28 October 2014 through 31 October 2014

ER -

Pao CC, Chen YC, Tsai CH. Top-down methodology based low-dropout regulator design using Verilog-A. 於 Zhou J, Tang TA, 編輯, Proceedings - 2014 IEEE 12th International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2014. Institute of Electrical and Electronics Engineers Inc. 2014. 7021500. (Proceedings - 2014 IEEE 12th International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2014). doi: 10.1109/ICSICT.2014.7021500

Top-down methodology based low-dropout regulator design using Verilog-A

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