Top-down methodology based low-dropout regulator design using Verilog-A

Chia Cheng Pao, Yan Chih Chen, Chien-Hung Tsai

研究成果: Conference contribution

2 引文 斯高帕斯(Scopus)

摘要

This paper presents a top-down design methodology, which adopts the analog modeling methodology and mixed-level simulation strategy together, for low-dropout regulators (LDO) with low ESR output capacitor. The proposed methodology helps designers to verify the sub-block specifications before designing transistors and reduce design iterations, benefiting cost optimization. All the macro-models are developed in Verilog-A under a Cadence Spectre platform and used in the design flow. A design case implemented in TSMC 0.35μm CMOS technology is presented that shows how this methodology supports system design. Simulation and measurement results expose high similarity, making it a useful and efficient way for LDO design.

原文English
主出版物標題Proceedings - 2014 IEEE 12th International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2014
編輯Jia Zhou, Ting-Ao Tang
發行者Institute of Electrical and Electronics Engineers Inc.
ISBN(電子)9781479932962
DOIs
出版狀態Published - 2014 一月 23
事件2014 12th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2014 - Guilin, China
持續時間: 2014 十月 282014 十月 31

出版系列

名字Proceedings - 2014 IEEE 12th International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2014

Other

Other2014 12th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2014
國家China
城市Guilin
期間14-10-2814-10-31

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering
  • Computer Science Applications

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