Topological cell compaction via transistor rotation

L. Y. Wang; Y. T. Lai; B. D. Liu

Topological cell compaction via transistor rotation

L. Y. Wang, Y. T. Lai, B. D. Liu

電機工程學系

研究成果: Paper › 同行評審

摘要

In this paper we propose a new algorithm for layout compaction by modifying the topology of a given layout. Different from most compaction algorithms which move the components of a layout, our algorithm compacts a layout by changing the orientations of transistors. A set of operations including moving, adding, deleting, shrinking, extending, etc., can work on the wires to rebuild and compact the layout after rotating a transistor. The simulated annealing technique is adopted in our algorithm to find a near optimal solution.

原文	English
頁面	909-912
頁數	4
出版狀態	Published - 1991
事件	China 1991 International Conference on Circuits and Systems. Part 2 (of 2) - Shenzhen, China 持續時間: 1991 6月 16 → 1991 6月 17

Other

Other	China 1991 International Conference on Circuits and Systems. Part 2 (of 2)
城市	Shenzhen, China
期間	91-06-16 → 91-06-17

All Science Journal Classification (ASJC) codes

一般工程

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title = "Topological cell compaction via transistor rotation",

abstract = "In this paper we propose a new algorithm for layout compaction by modifying the topology of a given layout. Different from most compaction algorithms which move the components of a layout, our algorithm compacts a layout by changing the orientations of transistors. A set of operations including moving, adding, deleting, shrinking, extending, etc., can work on the wires to rebuild and compact the layout after rotating a transistor. The simulated annealing technique is adopted in our algorithm to find a near optimal solution.",

author = "Wang, {L. Y.} and Lai, {Y. T.} and Liu, {B. D.}",

year = "1991",

language = "English",

pages = "909--912",

note = "China 1991 International Conference on Circuits and Systems. Part 2 (of 2) ; Conference date: 16-06-1991 Through 17-06-1991",

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TY - CONF

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AU - Wang, L. Y.

AU - Lai, Y. T.

AU - Liu, B. D.

PY - 1991

Y1 - 1991

N2 - In this paper we propose a new algorithm for layout compaction by modifying the topology of a given layout. Different from most compaction algorithms which move the components of a layout, our algorithm compacts a layout by changing the orientations of transistors. A set of operations including moving, adding, deleting, shrinking, extending, etc., can work on the wires to rebuild and compact the layout after rotating a transistor. The simulated annealing technique is adopted in our algorithm to find a near optimal solution.

AB - In this paper we propose a new algorithm for layout compaction by modifying the topology of a given layout. Different from most compaction algorithms which move the components of a layout, our algorithm compacts a layout by changing the orientations of transistors. A set of operations including moving, adding, deleting, shrinking, extending, etc., can work on the wires to rebuild and compact the layout after rotating a transistor. The simulated annealing technique is adopted in our algorithm to find a near optimal solution.

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UR - http://www.scopus.com/inward/citedby.url?scp=0026262542&partnerID=8YFLogxK

M3 - Paper

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T2 - China 1991 International Conference on Circuits and Systems. Part 2 (of 2)

Y2 - 16 June 1991 through 17 June 1991

ER -

Topological cell compaction via transistor rotation

摘要

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All Science Journal Classification (ASJC) codes

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