Towards logic functions as the device

Prasad Shabadi, Alexander Khitun, Pritish Narayanan, Mingqiang Bao, Israel Koren, Kang L. Wang, C. Andras Moritz

研究成果: Conference contribution

29 引文 斯高帕斯(Scopus)

摘要

This paper argues for alternate state variables and new types of sophisticated devices that implement more functionality in one computational step than typical devices based on simple switches. Elementary excitations in solids enabling wave interactions are possible initial candidates to create such new devices. The paper focuses on magnon-based spin-wave-logic functions (SPWF) and presents high fan-in majority, weighted high fan-in majority, and frequency-multiplexed weighted high fan-in majority devices as initial SPWFs. Experiments proving feasibility are also shown. Benefits vs. scaled CMOS are quantified. Results show that for 128 or larger inputs even a 2.5μm SPWF carry-look-ahead adder implementation is faster than the 45nm CMOS version. The 45nm SPWF adder is expected to be significantly faster across the whole range of input widths. In particular, the 45nm SPWF CLA adder is estimated to be at least 77X faster than CMOS version for input widths equal to or greater than 1024. A second example of a counter circuit is presented to illustrate the considerable reduction in complexity possible vs. CMOS.

原文English
主出版物標題Proceedings of the 2010 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2010
頁面11-16
頁數6
DOIs
出版狀態Published - 2010
事件2010 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2010 - Anaheim, CA, United States
持續時間: 2010 6月 172010 6月 18

出版系列

名字Proceedings of the 2010 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2010

Conference

Conference2010 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2010
國家/地區United States
城市Anaheim, CA
期間10-06-1710-06-18

All Science Journal Classification (ASJC) codes

  • 硬體和架構
  • 電氣與電子工程

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