Towards optimized packet processing for multithreaded network processor

Yeim-Kuan Chang, Fang Chen Kuo

研究成果: Conference contribution

2 引文 斯高帕斯(Scopus)

摘要

With the evolution of the Internet, current routers need to support a variety of emerging network applications while the high packet processing rate is still guaranteed. As a result, the network processor has become a promising solution for network devices due to its computation capability and programming flexibility. However, developing the network applications on network processors is not easy. How to efficiently program multiple processing elements and utilize various memory modules as well as the hardware resources on network processors are always challenges. In this paper, we investigate several optimization issues and programming techniques that should be considered by the developers to achieve higher packet processing rate on network processors. We use an existing packet classification scheme called hierarchical binary prefix search (HBPS) [I] as the benchmark to test and evaluate these optimization techniques. The experiments conducted on Intel IXP2400 network processor show that the overall performance of HBPS can be improved about 42% while these techniques are adopted.

原文English
主出版物標題2010 International Conference on High Performance Switching and Routing, HPSR 2010
頁面127-132
頁數6
DOIs
出版狀態Published - 2010 11月 12
事件2010 International Conference on High Performance Switching and Routing, HPSR 2010 - Richardson, TX, United States
持續時間: 2010 6月 132010 6月 16

出版系列

名字2010 International Conference on High Performance Switching and Routing, HPSR 2010

Other

Other2010 International Conference on High Performance Switching and Routing, HPSR 2010
國家/地區United States
城市Richardson, TX
期間10-06-1310-06-16

All Science Journal Classification (ASJC) codes

  • 電腦網路與通信
  • 硬體和架構

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