Transaction level modeling and design space exploration for SOC test architectures

Chin Yao Chang, Chih Yuan Hsiao, Kuen-Jong Lee, Alan P. Su

研究成果: Conference contribution

2 引文 (Scopus)

摘要

Transaction level modeling (TLM) provides a feasible methodology to model an SOC at a high abstraction level such that system level design issues can be dealt with efficiently. One of the issues that have not been well discussed at the transaction level is SOC testing. In this paper we address the problem of how to construct transaction level test architectures for SOC designs. We model the components required for SOC testing including embedded processor, memory, system bus as well as the test access mechanism, test bus, test wrappers and scan-or BIST-based IP cores. A case study on integrating these components into a test platform that can execute test procedures with very little external controlis carried out. Experimental results show that 3 to 4 orders of magnitude improvement on simulation speed can be achieved compared with the RTL models. We also explore the designspace of the test platform and show that various test architectures can be easily constructed and analyzed with this TLM methodology.

原文English
主出版物標題Proceedings of the 18th Asian Test Symposium, ATS 2009
頁面200-205
頁數6
DOIs
出版狀態Published - 2009 十二月 1
事件18th Asian Test Symposium, ATS 2009 - Taichung, Taiwan
持續時間: 2009 十一月 232009 十一月 26

出版系列

名字Proceedings of the Asian Test Symposium
ISSN(列印)1081-7735

Other

Other18th Asian Test Symposium, ATS 2009
國家Taiwan
城市Taichung
期間09-11-2309-11-26

指紋

System buses
Built-in self test
Testing
Program processors
Data storage equipment
Intellectual property core

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

引用此文

Chang, C. Y., Hsiao, C. Y., Lee, K-J., & Su, A. P. (2009). Transaction level modeling and design space exploration for SOC test architectures. 於 Proceedings of the 18th Asian Test Symposium, ATS 2009 (頁 200-205). [5359358] (Proceedings of the Asian Test Symposium). https://doi.org/10.1109/ATS.2009.33
Chang, Chin Yao ; Hsiao, Chih Yuan ; Lee, Kuen-Jong ; Su, Alan P. / Transaction level modeling and design space exploration for SOC test architectures. Proceedings of the 18th Asian Test Symposium, ATS 2009. 2009. 頁 200-205 (Proceedings of the Asian Test Symposium).
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Chang, CY, Hsiao, CY, Lee, K-J & Su, AP 2009, Transaction level modeling and design space exploration for SOC test architectures. 於 Proceedings of the 18th Asian Test Symposium, ATS 2009., 5359358, Proceedings of the Asian Test Symposium, 頁 200-205, 18th Asian Test Symposium, ATS 2009, Taichung, Taiwan, 09-11-23. https://doi.org/10.1109/ATS.2009.33

Transaction level modeling and design space exploration for SOC test architectures. / Chang, Chin Yao; Hsiao, Chih Yuan; Lee, Kuen-Jong; Su, Alan P.

Proceedings of the 18th Asian Test Symposium, ATS 2009. 2009. p. 200-205 5359358 (Proceedings of the Asian Test Symposium).

研究成果: Conference contribution

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Chang CY, Hsiao CY, Lee K-J, Su AP. Transaction level modeling and design space exploration for SOC test architectures. 於 Proceedings of the 18th Asian Test Symposium, ATS 2009. 2009. p. 200-205. 5359358. (Proceedings of the Asian Test Symposium). https://doi.org/10.1109/ATS.2009.33