摘要
Transaction level modeling (TLM) provides a feasible methodology to model an SOC at a high abstraction level such that system level design issues can be dealt with efficiently. One of the issues that have not been well discussed at the transaction level is SOC testing. In this paper we address the problem of how to construct transaction level test architectures for SOC designs. We model the components required for SOC testing including embedded processor, memory, system bus as well as the test access mechanism, test bus, test wrappers and scan-or BIST-based IP cores. A case study on integrating these components into a test platform that can execute test procedures with very little external controlis carried out. Experimental results show that 3 to 4 orders of magnitude improvement on simulation speed can be achieved compared with the RTL models. We also explore the designspace of the test platform and show that various test architectures can be easily constructed and analyzed with this TLM methodology.
| 原文 | English |
|---|---|
| 主出版物標題 | Proceedings of the 18th Asian Test Symposium, ATS 2009 |
| 頁面 | 200-205 |
| 頁數 | 6 |
| DOIs | |
| 出版狀態 | Published - 2009 十二月 1 |
| 事件 | 18th Asian Test Symposium, ATS 2009 - Taichung, Taiwan 持續時間: 2009 十一月 23 → 2009 十一月 26 |
出版系列
| 名字 | Proceedings of the Asian Test Symposium |
|---|---|
| ISSN（列印） | 1081-7735 |
Other
| Other | 18th Asian Test Symposium, ATS 2009 |
|---|---|
| 國家 | Taiwan |
| 城市 | Taichung |
| 期間 | 09-11-23 → 09-11-26 |
指紋
All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering
引用此文
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Transaction level modeling and design space exploration for SOC test architectures. / Chang, Chin Yao; Hsiao, Chih Yuan; Lee, Kuen-Jong; Su, Alan P.
Proceedings of the 18th Asian Test Symposium, ATS 2009. 2009. p. 200-205 5359358 (Proceedings of the Asian Test Symposium).研究成果: Conference contribution
TY - GEN
T1 - Transaction level modeling and design space exploration for SOC test architectures
AU - Chang, Chin Yao
AU - Hsiao, Chih Yuan
AU - Lee, Kuen-Jong
AU - Su, Alan P.
PY - 2009/12/1
Y1 - 2009/12/1
N2 - Transaction level modeling (TLM) provides a feasible methodology to model an SOC at a high abstraction level such that system level design issues can be dealt with efficiently. One of the issues that have not been well discussed at the transaction level is SOC testing. In this paper we address the problem of how to construct transaction level test architectures for SOC designs. We model the components required for SOC testing including embedded processor, memory, system bus as well as the test access mechanism, test bus, test wrappers and scan-or BIST-based IP cores. A case study on integrating these components into a test platform that can execute test procedures with very little external controlis carried out. Experimental results show that 3 to 4 orders of magnitude improvement on simulation speed can be achieved compared with the RTL models. We also explore the designspace of the test platform and show that various test architectures can be easily constructed and analyzed with this TLM methodology.
AB - Transaction level modeling (TLM) provides a feasible methodology to model an SOC at a high abstraction level such that system level design issues can be dealt with efficiently. One of the issues that have not been well discussed at the transaction level is SOC testing. In this paper we address the problem of how to construct transaction level test architectures for SOC designs. We model the components required for SOC testing including embedded processor, memory, system bus as well as the test access mechanism, test bus, test wrappers and scan-or BIST-based IP cores. A case study on integrating these components into a test platform that can execute test procedures with very little external controlis carried out. Experimental results show that 3 to 4 orders of magnitude improvement on simulation speed can be achieved compared with the RTL models. We also explore the designspace of the test platform and show that various test architectures can be easily constructed and analyzed with this TLM methodology.
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U2 - 10.1109/ATS.2009.33
DO - 10.1109/ATS.2009.33
M3 - Conference contribution
AN - SCOPUS:77951149196
SN - 9780769538648
T3 - Proceedings of the Asian Test Symposium
SP - 200
EP - 205
BT - Proceedings of the 18th Asian Test Symposium, ATS 2009
ER -