Transaction level modeling and design space exploration for SOC test architectures

Transaction level modeling (TLM) provides a feasible methodology to model an SOC at a high abstraction level such that system level design issues can be dealt with efficiently. One of the issues that have not been well discussed at the transaction level is SOC testing. In this paper we address the problem of how to construct transaction level test architectures for SOC designs. We model the components required for SOC testing including embedded processor, memory, system bus as well as the test access mechanism, test bus, test wrappers and scan-or BIST-based IP cores. A case study on integrating these components into a test platform that can execute test procedures with very little external controlis carried out. Experimental results show that 3 to 4 orders of magnitude improvement on simulation speed can be achieved compared with the RTL models. We also explore the designspace of the test platform and show that various test architectures can be easily constructed and analyzed with this TLM methodology.