The digital low dropout (LDO) voltage regulator are widely used in digital circuits which has multiple power domain and large dynamic supply ranges in System on Chip (SoC) application. The closed-loop transfer function of digital LDO is hard to derive because of two factors. One is mixture of discrete- and continuous-time operation. The other is the nonlinear comparator gain. However, the availability of open-loop transfer function is also limited by the non-constant feedback factor. Therefore, the prediction of digital LDO performance in the early design stage is difficult. Moreover, designer cannot explore the design space effectively. This paper builds a time-domain behavior model in MATLAB/Simulink to estimate transient response performance of DLDO and voltage ripple in steady state. This paper avoid complex mathematical operations. The result of the estimation is compared with transistor level simulation by HSPICE.