Transient thermal analysis for board-level chip-scale packages subjected to coupled power and thermal cycling test conditions

Tong Hong Wang, Chang Chi Lee, Yl Shao Lai, Yu Cheng Lin

研究成果: Review article同行評審

14 引文 斯高帕斯(Scopus)

摘要

In this work, thermal characteristics of a board-level chip-scale package, subjected to coupled power and thermal cycling test conditions defined by JEDEC, are investigated through the transient thermal analysis. Tabular boundary conditions are utilized to deal with time-varying thermal boundary conditions brought by thermal cycling. It is obvious from the analysis that the presence of power cycling leads to a significant deviation of the junction temperature from the thermal cycling profile. However, for components away from the die, the deviation is insignificant. Moreover, for low-power applications, temperature histories from coupled power and thermal cycling are approximately linear combinations of temperature histories from pure power cycling and the ones from pure thermal cycling.

原文English
頁(從 - 到)281-284
頁數4
期刊Journal of Electronic Packaging, Transactions of the ASME
128
發行號3
DOIs
出版狀態Published - 2006 九月 1

All Science Journal Classification (ASJC) codes

  • 電子、光磁材料
  • 材料力學
  • 電腦科學應用
  • 電氣與電子工程

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