Transition-code based linearity test method for pipelined ADCs with digital error correction

Jin Fu Lin, Soon Jyh Chang, Te Chieh Kung, Hsin Wen Ting, Chih Hao Huang

研究成果: Article同行評審

22 引文 斯高帕斯(Scopus)

摘要

A transition-code based method is proposed to reduce the linearity testing time of pipelined analog-to-digital converters (ADCs). By employing specific architecture-dependent rules, only a few specific transition codes need to be measured to accomplish the accurate linearity test of a pipelined ADC. In addition, a simple digital Design-for-Test (DfT) circuit is proposed to help correctly detect transition codes corresponding to each pipelined stage. With the help of the DfT circuit, the proposed method can be applied for pipelined ADCs with digital error correction (DEC). Experimental results of a practical chip show that the proposed method can achieve high test accuracy for a 12-bit 1.5-bit/stage pipelined ADC with different nonlinearities by measuring only 9.3% of the total measured samples of the conventional histogram based method.

原文English
文章編號5648403
頁(從 - 到)2158-2169
頁數12
期刊IEEE Transactions on Very Large Scale Integration (VLSI) Systems
19
發行號12
DOIs
出版狀態Published - 2011 12月

All Science Journal Classification (ASJC) codes

  • 軟體
  • 硬體和架構
  • 電氣與電子工程

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