Two-stage hot-carrier-induced degradation of p-type LDMOS transistors

Jone-Fang Chen, Tzu Hsiang Chen, Deng Ren Ai

研究成果: Article

3 引文 (Scopus)

摘要

Hot-carrier-induced device degradation of high-voltage p-type lateral diffused metal-oxide semiconductor (LDMOS) transistors is investigated. A two-stage linear region drain current (IDlin) shift (IDlin shift increases rapidly at the beginning of stress but tends to saturate when the stress time is longer) is observed. Technology computer-aided-design simulations and direct current current-voltage measurement results suggest that the decrease of residual fabrication interface traps (NIT) leads to an initial increase in IDlin shift. On the other hand, two competing mechanisms, i.e. increase in NIT generation and increase in electron trapping, are responsible for the saturated IDlin shift when the stress time is longer.

原文English
頁(從 - 到)1751-1753
頁數3
期刊Electronics Letters
50
發行號23
DOIs
出版狀態Published - 2014 十一月 6

指紋

Hot carriers
Transistors
Degradation
Metals
Drain current
Voltage measurement
Electric current measurement
Computer aided design
Fabrication
Electrons
Electric potential
Oxide semiconductors

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

引用此文

Chen, Jone-Fang ; Chen, Tzu Hsiang ; Ai, Deng Ren. / Two-stage hot-carrier-induced degradation of p-type LDMOS transistors. 於: Electronics Letters. 2014 ; 卷 50, 編號 23. 頁 1751-1753.
@article{9224a5102d214970bd9ae97ab661395b,
title = "Two-stage hot-carrier-induced degradation of p-type LDMOS transistors",
abstract = "Hot-carrier-induced device degradation of high-voltage p-type lateral diffused metal-oxide semiconductor (LDMOS) transistors is investigated. A two-stage linear region drain current (IDlin) shift (IDlin shift increases rapidly at the beginning of stress but tends to saturate when the stress time is longer) is observed. Technology computer-aided-design simulations and direct current current-voltage measurement results suggest that the decrease of residual fabrication interface traps (NIT) leads to an initial increase in IDlin shift. On the other hand, two competing mechanisms, i.e. increase in NIT generation and increase in electron trapping, are responsible for the saturated IDlin shift when the stress time is longer.",
author = "Jone-Fang Chen and Chen, {Tzu Hsiang} and Ai, {Deng Ren}",
year = "2014",
month = "11",
day = "6",
doi = "10.1049/el.2014.2901",
language = "English",
volume = "50",
pages = "1751--1753",
journal = "Electronics Letters",
issn = "0013-5194",
publisher = "Institution of Engineering and Technology",
number = "23",

}

Two-stage hot-carrier-induced degradation of p-type LDMOS transistors. / Chen, Jone-Fang; Chen, Tzu Hsiang; Ai, Deng Ren.

於: Electronics Letters, 卷 50, 編號 23, 06.11.2014, p. 1751-1753.

研究成果: Article

TY - JOUR

T1 - Two-stage hot-carrier-induced degradation of p-type LDMOS transistors

AU - Chen, Jone-Fang

AU - Chen, Tzu Hsiang

AU - Ai, Deng Ren

PY - 2014/11/6

Y1 - 2014/11/6

N2 - Hot-carrier-induced device degradation of high-voltage p-type lateral diffused metal-oxide semiconductor (LDMOS) transistors is investigated. A two-stage linear region drain current (IDlin) shift (IDlin shift increases rapidly at the beginning of stress but tends to saturate when the stress time is longer) is observed. Technology computer-aided-design simulations and direct current current-voltage measurement results suggest that the decrease of residual fabrication interface traps (NIT) leads to an initial increase in IDlin shift. On the other hand, two competing mechanisms, i.e. increase in NIT generation and increase in electron trapping, are responsible for the saturated IDlin shift when the stress time is longer.

AB - Hot-carrier-induced device degradation of high-voltage p-type lateral diffused metal-oxide semiconductor (LDMOS) transistors is investigated. A two-stage linear region drain current (IDlin) shift (IDlin shift increases rapidly at the beginning of stress but tends to saturate when the stress time is longer) is observed. Technology computer-aided-design simulations and direct current current-voltage measurement results suggest that the decrease of residual fabrication interface traps (NIT) leads to an initial increase in IDlin shift. On the other hand, two competing mechanisms, i.e. increase in NIT generation and increase in electron trapping, are responsible for the saturated IDlin shift when the stress time is longer.

UR - http://www.scopus.com/inward/record.url?scp=84912061600&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84912061600&partnerID=8YFLogxK

U2 - 10.1049/el.2014.2901

DO - 10.1049/el.2014.2901

M3 - Article

AN - SCOPUS:84912061600

VL - 50

SP - 1751

EP - 1753

JO - Electronics Letters

JF - Electronics Letters

SN - 0013-5194

IS - 23

ER -