Hot-carrier-induced device degradation of high-voltage p-type lateral diffused metal-oxide semiconductor (LDMOS) transistors is investigated. A two-stage linear region drain current (IDlin) shift (IDlin shift increases rapidly at the beginning of stress but tends to saturate when the stress time is longer) is observed. Technology computer-aided-design simulations and direct current current-voltage measurement results suggest that the decrease of residual fabrication interface traps (NIT) leads to an initial increase in IDlin shift. On the other hand, two competing mechanisms, i.e. increase in NIT generation and increase in electron trapping, are responsible for the saturated IDlin shift when the stress time is longer.
All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering