Ultra-Low Standby Power SRAM with Adaptive Data-Retention-Voltage-Regulating Scheme

Chi Ray Huang, Kuan Lin Wu, Chung Han Wu, Lih Yih Chiou

研究成果: Conference contribution

摘要

Leakage power dissipation has become a major problem in advanced process technologies, especially in large SRAM designs. The use of adaptive techniques is a promising approach to decreasing power consumption through dynamic scaling of the supply voltage of integrated circuits. To obtain maximum reduction in leakage power, an adaptive data retention voltage (DRV)-regulating scheme is proposed to achieve substantial saving of SRAM standby power. The proposed design supports DRV operation from the above-threshold to subthreshold regions and self-adapts to process, voltage, and temperature variations by using the proposed DRV monitor. According to the measurement results, the proposed design using 90 nm CMOS technology exhibits maximum leakage savings of 71.5%.

原文English
主出版物標題2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 - Proceedings
發行者Institute of Electrical and Electronics Engineers Inc.
ISBN(電子)9781538648810
DOIs
出版狀態Published - 2018 四月 26
事件2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 - Florence, Italy
持續時間: 2018 五月 272018 五月 30

出版系列

名字Proceedings - IEEE International Symposium on Circuits and Systems
2018-May
ISSN(列印)0271-4310

Other

Other2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018
國家Italy
城市Florence
期間18-05-2718-05-30

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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