Ultrathin DPN STI SiON liner for 40 nm low-power CMOS technology

At sub-40 nm CMOS technology nodes, the implementation of shallow trench isolation (STI) becomes more challenging due to shrinking geometries and stricter device leakage requirements. As device geometries are shrinking, STI liner is also becoming thinner and plays an important role for the minimal consumption of device active area while effectively rounding the STI corner and minimizing stress-induced defects. Consequently, STI stress is enhanced by the scaling of STI-pitch, the volume expansion induced by STI liner and film stress of filling materials. This paper discusses the benefits of SiON liner growth by decoupled-plasma-nitridation (DPN) and SiON liner induced stress compared to conventional pure oxide liner growth by in situ steam generation (ISSG). Thin STI SiON liner offers lower sub-threshold leakage current without drive current loss for transistor performance. Moreover, junction leakage current is also reduced with scaling device active area. Thus, better device performance results in better minimum operation voltage (Vcc_min) of low-power 6T-SRAM. This paper demonstrates the influences of thin STI SiON liner growth by DPN in STI manufacture.