Unified architectural tradeoff methodology

Chung-Ho Chen, Arun K. Somani

研究成果: Conference article同行評審

4 引文 斯高帕斯(Scopus)


We present a unified approach to assess the trade-off of architecture techniques that affect mean memory access time. The architectural features we consider include cache hit ratio, processor stalling features, line size, memory cycle time, the external data bus width of a processor, pipelined memory system, and read by-passing write buffers. We demonstrate how each of these features can be traded off to achieve the desired performance. The performance of an architecture feature is quantified in terms of cache hit ratio based on the equivalence of mean memory delay time. This paper investigates the implication of architectural tradeoffs on the pin count, memory system design, and on-chip cache area for microprocessor systems.

頁(從 - 到)348-357
期刊Conference Proceedings - Annual International Symposium on Computer Architecture, ISCA
出版狀態Published - 1994 一月 1
事件Proceedings of the 21st Annual International Symposium on Computer Architecture - Chicago, IL, USA
持續時間: 1994 四月 181994 四月 21

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture

指紋 深入研究「Unified architectural tradeoff methodology」主題。共同形成了獨特的指紋。