Unified VLSI systolic array design for LZ data compression

Shih Arn Hwang, Cheng Wen Wu

研究成果: Article同行評審

13 引文 斯高帕斯(Scopus)

摘要

Hardware implementation of data compression algorithms is receiving increasing attention due to exponentially expanding network traffic and digital data storage usage. In this paper, we propose several serial one-dimensional and parallel two-dimensional systolic-arrays for Lempel-Ziv data compression. A VLSI chip implementing our optimal linear array is fabricated and tested. The proposed array architecture is scalable. Also, multiple chips (linear arrays) can be connected in parallel to implement the parallel array structure and provide a proportional speedup.

原文English
頁(從 - 到)489-499
頁數11
期刊IEEE Transactions on Very Large Scale Integration (VLSI) Systems
9
發行號4
DOIs
出版狀態Published - 2001 八月 1

All Science Journal Classification (ASJC) codes

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering

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